The technology described in this disclosure relates generally to semiconductor devices and more particularly to fabrication of semiconductor devices.
As feature sizes of semiconductor devices continue to shrink (e.g., into a sub 50 nm regime), various problems, such as short-channel effects and poor sub-threshold characteristics, often become severe in traditional planar devices. Novel device geometries, such as gate-all-around (GAA) devices, with enhanced performance are needed to push toward higher packing densities in devices and circuits.